1. Field of the Invention
This invention relates to phase synchronizing circuits, and more particularly to a phase synchronizing circuit in a device for reproducing data signals from recording media.
2. Background Art
When data signals are read out of a recording medium, such as a video disk rotating at a uniform speed, the time axis of the read signals is shifted, adversely affecting the reproduced images. Time axis shift is caused by the eccentricity of the recording medium or irregular rotation of the rotating mechanism.
In a method extensively employed to eliminate this time axis shift, a pulse signal synchronous with the time axis shift of the reproducing signal is formed, the reproducing signal is loaded in a memory with the synchronous pulse signal and then read with a frequency stable reference pulse signal. FIG. 1 shows a conventional phase synchronizing circuit for producing a pulse signal synchronous with the time axis shift of a reproducing signal in a time axis correcting system. In FIG. 1, a video signal, such as producing by a video disk, is applied to a reference signal detecting circuit 1 comprising a synchronizing separator circuit or the like, in which a horizontal synchronizing signal is separated from the video signal and outputted as a reproducing reference signal a. The reference signal detecting circuit 1 may be so designed that a pulse signal produced at a particular zero crossing point of the burst signal in the video signal is outputted as the reproducing reference signal.
The reproducing reference signal a outputted by the reference signal detecting circuit 1 is supplied to a phase comparison circuit 2, which also received the output d of a frequency division counter 4. The counter 4 subjects the output of a VCO (voltage controlled oscillator) 3 to 1/N frequency division. Thus, in the phase comparison circuit 2, the phase of the output d is compared with that of the reproducing reference signal a, and an error signal corresponding to the phase difference between the signals is formed by a sampling control system. That is, the phase comparison circuit 2 forms a saw tooth signal with the aid of the output d of the frequency division counter 4, and outputs the error signal b, obtained by sampling and holding the saw tooth signal in response to the reproducing reference signal a. The error signal b is applied, as a control signal, to the VCO 3, which outputs a clock pulse c synchronous with the time axis variation of the reproducing reference signal a.
The above-described phase synchronizing circuit is advantageous in that it is simple in arrangement and stable in operation. That is, when the frequency division ratio of the frequency division counter 4 is set to N, the oscillation frequency of the VCO is N.multidot.f.sub.H, where f.sub.H is the horizontal synchronizing frequency. However, this conventional circuit is disadvantageous in that it cannot immediately respond to an abrupt phase change of the reproducing reference signal a. In order to allow the circuit to quickly respond to an abrupt phase change, it is necessary to increase the loop band. However, in the sampling control system in which the reproducing reference signal is inputted with a period of 1H (63.5 .mu.s), the loop band is limited because of the phase lag.
If the phase synchronizing circuit has a slow response time, then when broadcasting VTR, the follow-up characteristic with the phase jump of a reproducing horizontal synchronizing signal due to a skew failure or with the phase variation or a reproducing horizontal synchronizing signal in a special reproduction mode becomes slow. Therefore, the time axis correcting capacity is reduced. In the case of a video disk, an image memory is utilized so that, even with a constant linear velocity (CLV) disk, a special reproduction such as a still picture reproduction can be achieved. However, if the VCO does not immediately respond to the phase discontinuation of the reproducing horizontal synchronizing signal which is caused by a track jumping operation, then the picture reproduced on the TV monitor has irregular color or appears distorted or out of synchronization. This will be described in more detail.
When as shown in FIG. 2, a track jumping operation occurs on playing a CLV disk (shown at time instant t.sub.1), the error signal b outputted by the phase comparison circuit 2 is irregular for a period of time, t.sub.1 to t.sub.2. This results because, even if the phase of the reproducing reference signal a is coincident with that of the output d of the frequency division counter 4 before the time instant t.sub.1, as shown in FIG. 3, the track jump breaks the continuation of the reproducing reference signal a. As a result, as shown in FIG. 4, the phase of the reproducing reference signal a is shifted from that of the output d of the frequency division counter 4. The VCO 3 is closed-loop-controlled with a sample value taken every 1 H. Therefore, even if the loop characteristic is improved, the time required for convergence of the phase shift is limited. Accordingly, for the period of time (t.sub.1 to t.sub.2) in which the phase error is large, writing data into the image memory should be inhibited. However, if the track jumping operation is repeatedly carried out within a short period, the time period in which the phase error is in coincidence is decreased, so that it becomes impossible to write data in the image memory. That is, it is impossible to achieve the desired special reproduction with high accuracy.
One example of a conventional phase synchronizing circuit with an excellent response characteristics is shown in FIG. 5. In FIG. 5, a reference signal detecting circuit 1 outputs a reproducing reference signal a, which is applied to a frequency-synchronized control circuit 5 and applied, as a reset signal, to a VCO 3. In the circuit 5, the reproducing reference signal a is compared with the output of the VCO, and an error signal corresponding to the frequency difference and phase difference between the two signals is formed. The error signal thus formed is applied, as a control signal, to the VCO 3. The circuit of FIG. 5 is controlled so that the frequency ratio of the reproducing reference signal a to the output clock signal of the VCO 3 is a predetermined value. Under this condition, the phase of the VCO 3 is reset by the reproducing reference signal every other 1H (horizontal line period). Owing to this phase resetting operation, the phase and frequency of the clock signal outputted by the VCO 3 are immediately set to predetermined values. This means that the circuit has an excellent response characteristic. However, this conventional phase synchronizing circuit suffers from the following disadvantage. Frequency control is carried out in the circuit, and therefore the oscillation frequency of the VCO may be locked at a frequency (N+1).multidot.f.sub.H or (N-1).multidot.f.sub.H as well as the above-described frequency N.multidot.f.sub.H. Accordingly, the frequency-synchronized control circuit 5 should be designed to prevent this phenomenon. Therefore, this conventional phase synchronzizing circuit has unavoidably intricate circuitry.